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Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits

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2 Author(s)
Ja Chun Ku ; Northwestern Univ., Evanston ; Yehea Ismail

In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:15 ,  Issue: 8 )