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A Pulsed Low-Voltage Swing Latch for Reduced Power Dissipation in High-Frequency Microprocessors

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6 Author(s)
Pong-Fei Lu ; IBM T. J. Watson Res. Center, Yorktown Heights, NY ; Nianzheng Caon ; Sigal, L. ; Woltgens, P.
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We have reported previously (Pong-Fei Lu et al., 2004) a low-swing latch (LSL) with superior performance-power tradeoff compared to the conventional pass-gate master-slave latch. In this paper, hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system power in high-frequency microprocessors. We have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle between two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system power saving can be achieved in pulsed mode compared to non-pulsed mode. Power contribution from individual components is also presented

Published in:

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Date of Conference:

4-6 Oct. 2006