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Robust Level Converter Design for Sub-threshold Logic

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3 Author(s)
Ik Joon Chang ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN ; Jae-Joon Kim ; Roy, K.

The large supply voltage difference between sub-threshold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, clock synchronizer and reduced swing inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500kHz between 20degC and 40degC with a supply voltage of 0.25V

Published in:

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Date of Conference:

4-6 Oct. 2006

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