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Plasma dry etching processes are commonly used to fabricate vertical sidewall trenches and vias for copper (Cu)/low-k dual damascene devices. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the dry etching process in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Other particulate etch residues (such as mixtures of copper oxide (CuxOy) with polymers) can be seen in the bottom of the vias. As technology nodes advance to 45 nm and beyond, IC companies are investigating the use of a metal hardmask such as TiN in order to gain better etching selectivity to the low-k materials during the dry etching process. In order to obtain reliable, low-resistance interconnects that can be used to manufacture advanced IC devices, the polymers on the sidewalls and the particulate residues at the via bottoms must be removed prior to the next process step. In this paper we report a recently developed wet cleaning approach to remove the metal hardmask etch residues while maintaining high selectivity to the copper and low-k film(s). This was demonstrated at the 45 nm technology node for porous low-k, as well as 65 nm for non-porous low-k materials through controlled modification of the formulations. The cleaning mechanism of the etch residues is discussed.