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For the scaling down of design rule to develop the high density NAND flash device, the reduced active area forces to form a small bit-line contact with the low contact-resistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to make 38 nm small size contact with 76 nm pitch by using the reversal PR (photo resist) and SADP (self-align double patterning) process. The methods to minimize the contact resistance and to suppress the junction leakage current were explained on NAND flash device with 38 nm node technology.
Date of Conference: 11-12 June 2007