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A Novel P-Poly Gate PNOS Device Featuring High 2nd-Bit Operation Window for Multi-bit/cell Flash Memory Applications

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8 Author(s)
Jau-Yi Wu ; Emerging Central Lab., Macronix International Co., Ltd. No. 16, Li-Hsin Road, Science Park, Hsinchu, Taiwan, R.O.C., Email:, Fax: 886-3-5789087; Phone: 886-3-5786688 ; Ming-Chang Kuo ; Chao-Lun Yu ; Tzu-Hsuan Hsu
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A novel PNOS (P-poly Nitride-Oxide-Si) device that exploits gate edge assisted hole injection is proposed to reduce the 2nd-bit effect. The device is erased by gate hole injection and programmed by the usual CHE (channel hot electron). Holes are injected from the gate edge using +FN and trapped in the SiN that produce local negative Vt along the channel edge. This edge device in turn causes enhanced DIBL that helps to provide a large 2nd-bit window (> 4.5 V) that is suitable for MLC operation. Using this device, 4-bit/cell and 6-bit/cell operations are illustrated.

Published in:

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

Date of Conference:

23-25 April 2007