By Topic

The Effects of ONO thickness on Memory Characteristics in Nano-scale Charge Trapping Devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Moon Kyung Kim ; Department of Electrical and Computer Engineering Cornell University, Ithaca, NY 14853, ; SooDoo Chae ; Chung Woo Kim ; Jooyeon Kim
more authors

In the use of single/few electrons in distributed storage for nonvolatile, low power and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has a radicn dependence and we are working with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and evaluate the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of low doped drain (LDD) process is investigated to draw these conclusions.

Published in:

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

Date of Conference:

23-25 April 2007