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Systolic Array-Based Pipelining Design of CCK Demodulators

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2 Author(s)
Alan Y. W. Kok ; Ryerson Univ., Toronto ; K. L. Eddie Law

Complementary code keying (CCK) is one of the few channel coding techniques used in the widely deployed 802.11b wireless local area networks (WLANs). CCK is used for transmitting 5.5 and 11 Mbps data transfer rates. In this paper, we propose a design to improve the efficiency of CCK demodulation. The proposed systolic array architecture exploits and reuses the replicated butterfly structure of modified fast Walsh transform (MFWT). A typical MFWT CCK demodulator, consists of three stages, accepts all eight chips of the CCK codeword simultaneously, and outputs sixty-four values. Upon deploying the proposed systolic array design with its pipelining nature, instead of processing all eight chips of CCK in parallel during the first stage, every two chips can be processed immediately. At each stage, the results are moved instantly to the next stage upon multiplying the appropriate constants. This resulting systolic array architecture has many advantages over the conventional design. Firstly, a serial-to-parallel converter to convert serial incoming data to parallel blocks of eight chips is not required. This reduces hardware complexity. Secondly, every stage in the architecture is continuously processing data; whereas, in the conventional design, hardware in each stage is left idle after processing until inputs from the next eight chips block arrives. Thirdly, twenty-eight butterflies are needed in a conventional design, but, only thirteen butterflies are required due to hardware reuse in the proposed architecture.

Published in:

2007 Canadian Conference on Electrical and Computer Engineering

Date of Conference:

22-26 April 2007