3D-Vias Aware Quadratic Placement for 3D VLSI Circuits

This paper presents a cell placement algorithm for 3D-circuits. Compared to existing approaches, our placer has a number of new features that delivers more realism and improved wire length. First, the algorithm balances the tier utilization considering the effect of 3D-vias within two possible integration strategies: face-to-face and face-to-back. 3D-vias count is limited to an upper bound, that is sensible to the area of the 3D-via. Within the upper bound, the placer is free to add more 3D-vias, fact that delivers an improved wire length, as demonstrated experimentally in the paper. Our algorithm is based on a true 3D quadratic placement engine with a 3D cell shifting method to spread the cells out and on an iterative refinement step that improves wire length. Experimental results show that our algorithm can improve the wire length compared to a 2D solution provided by the FastPlace algorithm from 15% up to 27% in average.