Referenced Items are not available for this document.
Software developers can gain insight into software-hardware interactions by decomposing processor performance into individual cycles-per-instruction components that differentiate cycles consumed in active computation from those spent handling various miss events. Constructing accurate CPI components for out-of-order superscalar processors is complicated, however, because computation and miss event handling overlap. The authors' counter architecture, using an analytical superscalar performance model, handles overlap effects more accurately than existing methods
Published in:
Micro, IEEE
(Volume:27
,
Issue:
1
)
Date of Publication: Jan.-Feb. 2007
- Page(s):
- 84 - 93
- ISSN :
- 0272-1732
- INSPEC Accession Number:
- 9499100
- Digital Object Identifier :
- 10.1109/MM.2007.3
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 21 May 2007
- Issue Date :
- Jan.-Feb. 2007
- Sponsored by :
- IEEE Computer Society
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