Referenced Items are not available for this document.
As multicore chips become ubiquitous, the need to provide architectural support for practical parallel programming is reaching critical. Conventional lock-based concurrency control techniques are difficult to use, requiring the programmer to navigate through the minefield of coarse-versus fine-grained locks, deadlock, livelock, lock convoying, and priority inversion. This explicit management of concurrency is beyond the reach of the average programmer, threatening to waste the additional parallelism available with multicore architectures. This comprehensive architecture supports nested transactions, transactional handlers, and two-phase commit. The result is a seamless integration of transactional memory with modern programming languages and runtime environments
Published in:
Micro, IEEE
(Volume:27
,
Issue:
1
)
Date of Publication: Jan.-Feb. 2007
- Page(s):
- 67 - 76
- ISSN :
- 0272-1732
- INSPEC Accession Number:
- 9499098
- Digital Object Identifier :
- 10.1109/MM.2007.26
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 21 May 2007
- Issue Date :
- Jan.-Feb. 2007
- Sponsored by :
- IEEE Computer Society
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