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Enhancing delay fault coverage through low-power segmented scan

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5 Author(s)
Z. Zhang ; ECE Dept., Univ. of Iowa, IA ; S. M. Reddy ; I. Pomeranz ; J. Rajski
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Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low-power DFT techniques and test generation procedures have been proposed. Segmented scan has been shown to be an effective technique in addressing test power issues in industrial designs. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. For the first time, it has been demonstrated that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 and ITC-99 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 7.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 20.4%

Published in:

IET Computers & Digital Techniques  (Volume:1 ,  Issue: 3 )