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Scan cell design for launch-on-shift delay tests with slow scan enable

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2 Author(s)
G. Xu ; Electr. & Comput. Eng. Dept., Auburn Univ., AL ; A. D. Singh

Most scan-based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but requiring a fast scan enable. A low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge is presented. The new design is much more efficient when compared with other recent proposals and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve transition delay fault coverage approaching 95% for the ISCAS89 benchmarks

Published in:

IET Computers & Digital Techniques  (Volume:1 ,  Issue: 3 )