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A 1.5-V 3.2Gb/s/pin Graphic DDR4 SDRAM with Dual-Clock System, 4 Phase Input Strobing and Low Jitter Fully Analog DLL

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15 Author(s)

A 1.5V, 512 Mbit GDDR4 SDRAM using a 90-nm DRAM process has been developed. The data rate is 3.2 Gbps/pin, which corresponds to 12.8 GBps in x32 GDDR4 based I/O. A multi-divided architecture consisting of 4 independent 128 Mb core arrays is designed to reduce power and output noise. Also, a dual-clock system, 4 phase data input strobe scheme and 4 phase fully analog DLL are used to increase internal timing margins.

Published in:

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Date of Conference:

13-15 Nov. 2006