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Realizing Network on Chip Design of H.264 Decoder Based on Throughput Aware Mapping

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3 Author(s)
Vu-Duc Ngo ; Syst. VLSI Lab, Inf. & Commun. Univ., Daejeon, South Korea ; Huy-Nam Nguyen ; Hae-Wook Choi

A new chip design era in the coming nano-scale, so called network on chip (NoC), has been introduced based on the demand of the intensive use and seamless integration of many heterogeneous semiconductor intellectual property (IP) blocks in the form of embedded and distributed processors, memories, DSPs, and interfaces. The NoC design, with its own characteristics, very strictly requires the satisfaction of several physical constraints such as the network latency, the used area as well as the power consumption of design. In this paper, we introduce the queuing theory based and power model based of the router in order to analyzes the throughput, size and energy consumption of heterogeneous network on chip architectures. This article also presents the method to automatically map IPs onto the given architectures to obtain the maximum throughput while keep the minimum energy consumption. Some realizations of H.264 decoder on regular NoC architectures such as 2D mesh and fat-tree are simulated. The results show that the network throughput is maximized with the optimized mapping scheme. The energy dissipation consequently calculated and shown that it is very much saved compared to that of random mapping.

Published in:

Communications and Electronics, 2006. ICCE '06. First International Conference on

Date of Conference:

10-11 Oct. 2006