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Prioritized SMT Architecture with IPC Control Method for Real-Time Processing

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3 Author(s)
Nobuyuki Yamasaki ; Keio University, Japan ; Ikuo Magaki ; Tsutomu Itou

This paper describes a novel processor architecture, the prioritized SMT architecture with the IPC control method, to guarantee the execution time of real-time threads. Based on priority set by a real-time scheduler, all hardware resources including cache systems, fetch, issue, and execution units, are controlled, so that our processor can execute multiple threads in real-time. All runnable threads are simultaneously executed as much as possible in priority order, so that the execution order becomes congruent with the priority order set by a real-time scheduler. If a resource conflict occurs, the lower priority threads are kept waiting until the higher priority thread finishes using the resource. In brief, context switching required for real-time scheduling and execution is converted to the prioritized SMT execution. Here, some triggers including cache misses and branch prediction misses fluctuate the execution speed of a thread. Additionally, in case of an SMT processor, the execution time of each thread may vary according to a combination of simultaneous executing threads. To guarantee the execution time of real-time threads accurately, the IPC control method that monitors and controls each thread IPC in a feedback loop is designed and implemented. Our IPC control method can keep the IPC deviation of the thread within plusmn1% bounds, if the target IPC is less than 80% of the single thread execution IPC. Our processor is implemented as a processing core of a system LSI, which process was TSMC 0.13 mum 8 layered Cu wiring, used for distributed real-time systems including humanoid robots, bilateral robots, embedded control systems, and ubiquitous computing systems

Published in:

13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)

Date of Conference:

3-6 April 2007