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Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

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7 Author(s)
H. Fukutome ; Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo, 197-0833, Japan. Phone: +81-42-532-1250, Fax: +81-42-532-2513, E-mail: ; Y. Momiyama ; T. Kubo ; E. Yoshida
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We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)

Published in:

2006 International Electron Devices Meeting

Date of Conference:

11-13 Dec. 2006