By Topic

Space-Time Representation of Iterative Algorithms and the Design of Regular Processor Arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
E. D. Kyriakis-Bitzaros ; University of Patras, Greece ; O. G. Koufopavlou ; C. E. Goutis

A novel space-time representation of iterative algorithms, which can be expressed in nested loop form and may include non-constant dependencies is proposed and a systematic methodology for their mapping onto regular processor arrays is presented. In contrast to previous design methodologies, the execution time of any variable instance is explicitly expressed in the Dependence Graph, by the construction of the Space-Time Dependence Graph (STDG). This approach avoids the uniformization step of the algorithm and the requirement for fully indexing the variables.

Published in:

Parallel Processing, 1993. ICPP 1993. International Conference on  (Volume:3 )

Date of Conference:

16-20 Aug. 1993