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Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability

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3 Author(s)
Daniel GroBe ; Institute of Computer Science, University of Bremen, 28359 Bremen, Germany. grosse@informatik.uni-bremen.de ; Xiaobo Chen ; Rolf Drechsler

Compact synthesis result for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus we can guarantee minimality. For a set of benchmarks experimental results are given

Published in:

2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software

Date of Conference:

Oct. 2006