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Design and implementation of a reconfigurable heterogeneous multiprocessor SoC

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8 Author(s)
Massimo Bocchi ; ARCES, Advanced Research Center on Electronic Systems, University of Bologna, Italy ; Mario De Dominicis ; Claudio Mucci ; Antonio Deledda
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This paper introduces a novel heterogeneous shared memory multiprocessor architecture based on a reconfigurable processor and a standard RISC processor. The work aims at increasing further the computational density of a reconfigurable device by the integration of the reconfigurable hardware into a heterogeneous multi-core architecture. Though a RISC processor has a lower inner computational density than a reconfigurable processor, this work demonstrates that coupling a reconfigurable core to a RISC core leads to a computational density increase by a factor of up to 1.7times on signal processing applications. Moreover, this approach also achieves up to 37% energy savings on the same applications. The multi-core SoC architecture was implemented in 0.13mum technology, achieving a 166MHz clock frequency with an average 340mW power consumption

Published in:

IEEE Custom Integrated Circuits Conference 2006

Date of Conference:

10-13 Sept. 2006