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A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique

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4 Author(s)
Kanazawa, Y. ; Adv. Technol. Res. Labs., Sharp Corp., Nara ; Fujimoto, Y. ; Lo Re, P. ; Miyamoto, M.

A new ΔΣ ADC architecture using a triple sampling technique and a two-step summation scheme is presented. A 4th-order switched-capacitor ΔΣ ADC with a 4-bit quantizer is designed for a low-power direct-conversion digital TV receiver SoC. It achieves a 77.3-dB SNDR over a 4-MHz bandwidth with a 100-MHz clock frequency. The chip, fabricated in a 0.18-mum CMOS process, occupies 1.57 mm2 and draws 15.3 mA from a 1.8-V supply. It achieves a 0.58-pJ/conversion FOM

Published in:

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Date of Conference:

10-13 Sept. 2006

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