Referenced Items are not available for this document.
In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinck filters are also analyzed. Equations are derived for the estimation of the required number of cycles for a given resolution and architecture. Finally, the design and implementation of a third-order incremental converter with a fourth-order sine filter is briefly discussed
Published in:
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Date of Conference: 10-13 Sept. 2006
- Page(s):
- 41 - 48
- E-ISBN :
- 1-4244-0076-7
- Print ISBN:
- 1-4244-0075-9
- INSPEC Accession Number:
- 9454248
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2006.320960
- Product Type:
- Conference Publications
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