A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead

An important aspect of partial reconfiguration is reconfiguration overhead, which normally includes the runtime reconfiguration time and the static reconfiguration data storage space. Both of these costs are directly related to the size of the physical partial reconfiguration file. In this paper, the structure of partial reconfiguration bitstream file is exploited at the frame granularity level to develop a novel approach to minimize this problem. The structural features of the bitstream file are used to manage physical area resources to reduce the partial reconfiguration bitstream size. In this approach, instead of relying on the design tools' random placement, most of the logic resources are predetermined at specific physical positions based on several principles. The proposed methodology is evaluated on the Virtex II Pro platform. The result shows file sizes can be reduced up to 30% on a variety of designs compared to non-area managed configurations. The experiments also imply that even higher rates of reduction can be achieved on larger designs