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Executing Algorithms for Dynamic Dataflow Reconfigurable Hardware -The Operators Protocol

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2 Author(s)
Luiz e Silva, J. ; Dept. of Sao Paulo, Sao Paulo Univ. ; Marques, E.

The increase of the demand for computational capacity, flexibility and low power, have been the requisite to define parts of the application program, that can be executed direct into the hardware. This is one of the definition for reconfigurable computing, where a full processor and a reconfigurable hardware are totally inside of the same chip. Altera Nios and Xilinx Microblaze are examples of those systems. The dynamic dataflow model explores the parallelism in a natural form. This paper describe the protocol for synchronize the data into a dataflow graph implemented with XilinxregISE 8.2i as part of implementation of an dynamic dataflow graphs model, direct into the hardware. The result for "proof-of-concept" of the protocol is presented to the end of this paper

Published in:

Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on

Date of Conference:

Sept. 2006

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