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FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems

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4 Author(s)

The run-time reconfigurable (RTR) feature is highly desirable for flexible and fast self-contained systems. RTR can be achieved on some commercial FPGA platforms. We propose an open solution, called FASE that allows for fine-grain RTR, designed to be more intuitive than currently available solutions. The issues of initializing RTR soft IP-cores and a design flow to manage the dynamics of RTR are presented. In the context of secure embedded systems, there is a need for both flexibility and tamper-resistance. However, the robustness level for security constraints is difficult to get and to prove because of the proprietary hidden structures. The FASE architecture addresses these issues. It makes it possible for any designer to implement custom and arbitrary dynamic strategies. We illustrate two case studies: an implementation-level counter-measure against side-channel attacks and an efficient strategy to thwart fault injection attacks against cryptographic functions

Published in:

Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on

Date of Conference:

Sept. 2006