By Topic

Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Marcos Vinicius Da Silva ; Depto Informática, Universidade Federal de Viçosa, Cep 36570-000, Vicosa, Brazil; Núcleo de Ciências Exatas - UnilesteMG, CEP.: 35170-056, Coronel Fabriciano, Brazil ; Ricardo Ferreira ; Alisson Garcia ; Joao M. P. Cardoso

Coarse-grained reconfigurable array architectures are currently focus of intensive research. They have already proven performance improvements and energy savings over traditional architectures. However, coarse-grained arrays vary widely in the number and characteristics of the processing elements and routing topologies used. This work presents a flexible mapping environment for design space exploration of coarse-grained, data-driven, reconfigurable array architectures. The mapping included in the environment presented in this paper takes advantage of Java and XML technologies to enable an efficient architectural tradeoff analysis. This approach does not focus on neither a specific mapping algorithm nor a specific architecture, but on an open environment where users can add their own mapping algorithms and architecture patterns. A genetic algorithm for placement is presented. A number of DSP benchmarks are used to explore a range of mesh architectures and to validate the approach. The experiments show a fast, scalable and flexible mapping environment to explore new mesh array patterns, homogeneous and heterogeneous architectures

Published in:

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

Date of Conference:

20-22 Sept. 2006