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Scaling to 10 nm-bulk, SOI or double-gate MOSFETs?

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4 Author(s)
Minjian Liu ; Dept. of Electr. & Comput. Eng., California Univ., San Diego, CA ; Wei-Yuan Lu ; Wei Wang ; Yuan Taur

In this paper, we assess the potential for bulk CMOS, SOI CMOS, and double-gate CMOS to extend scaling to 10 nm channel length. In addition to the required replacement of silicon dioxide and polysilicon gates by high-k insulator and metal gates for all device types, specific technology requirements are discussed for each device type. 10 nm bulk CMOS requires abrupt placement of n- and p-type dopants at >1019 cm-3 levels for both the channel and the source-drain regions. 10 nm SOI CMOS requires the silicon film thickness to be scaled to its quantum limit of 2 nm. The silicon film thickness requirement is somewhat relaxed in a double-gate device structure. But the self-alignment requirement of a double-gate (or multi-gate) device makes it very challenging to realize a manufacturable process

Published in:

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Date of Conference:

23-26 Oct. 2006