Challenges for sub-10 nm CMOS devices
- Already Purchased? View Article
- Subscription Options Learn More
Sub-10nm CMOS devices are the critical issue, because CMOS scaling is going to be sub-25nm regime. Scaling issues of nano-size MOSFETs can be discussed on the basis of sub-10 nm MOSFETs characteristics, which have been developed and confirmed switching characteristics and low-temperature characteristics. Studying device limitation issues and developing new breakthrough technologies are required to challenge sub-10-nm CMOS devices
Published in:
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Date of Conference: 23-26 Oct. 2006