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High-Speed Arithmetic in Binary Computers

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1 Author(s)
O. L. Macsorley ; Product Dev. Lab., Data Systems Div., IBM Corp., Poughkeepsie, N.Y.

Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost. The transit time of a logical unit is used as a time base in comparing the operating speeds of different methods, and the number of individual logical units required is used in the comparison of costs. The methods described are logical and mathematical, and may be used with various types of circuits. The viewpoint is primarily that of the systems designer, and examples are included wherever doing so clarifies the application of any of these methods to a computer. Specific circuit types are assumed in the examples.

Published in:

Proceedings of the IRE  (Volume:49 ,  Issue: 1 )