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Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS

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9 Author(s)
V. P. Trivedi ; Austin Silicon Technology Solutions (ASTS), Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, MD: K-10, Austin, TX, 78721, (512) 933-3232, Fax: (512) 933-5076, ; G. S. Spencer ; P. Grudowski ; J. Liu
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Extrinsic source/drain series resistance (RSD/) becomes a limiting factor as performance boosters, such as strain-Si and metal-gate/high-k gate stack that enhance the intrinsic MOSFET, are vigorously pursued and implemented in nanoscale CMOS (Ghani, et al., 2003). Non-melt laser spike anneal (LSA) (Feng et al., 2004) has been suggested (Shima, et al., 2004), (Fung et al., 2004) as a means to reduce RSD/. In this paper, we present, for the first time, application of LSA to 35nm gate length, high-performance PD/SOI CMOS with dual etch stop layer (dESL) stressors and NiSi (Grudowski et al., 2006), showing 10% (4%) nFET (pFET) on-state current (Ion) enhancement and non-self-heated Ion=1520/1160muA/mum (880/630muA/mum) at VDD=1.2V/1.0V

Published in:

2006 IEEE international SOI Conferencee Proceedings

Date of Conference:

2-5 Oct. 2006