The author reviews some basic mechanical design approaches available to assure reliable interfaces within and between packaging levels in the chip, package, and circuit-board assemblies. While the approaches can be applied to traditional circuit-board and hybrid assemblies emphasis is placed on the hybrid wafer-scale integration multichip module packaging technologies. It is concluded that a combination of recently available packaging materials of improved properties, recently developed improved analysis techniques, and the advantages of the new hybrid wafer-scale integration technology offers the opportunity to design significantly improved reliability into the next generation of military electronic equipment. Additionally, the equipment size and weight can be reduced significantly. A dramatic demonstration of the miniaturization possible with these technologies was made on a miniaturized version of a GPS (global positioning system) receiver
Published in:
Aerospace and Electronics Conference, 1989. NAECON 1989., Proceedings of the IEEE 1989 National
Date of Conference: 22-26 May 1989