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A test chip design for detecting thin-film cracking in integrated circuits

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3 Author(s)
Gee, S.A. ; Nat. Semicond. Corp., Santa Clara, CA, USA ; Johnson, M.R. ; Chen, K.L.

A reliability problem associated with integrated circuit assembly in molded plastic packages involves cracking in the deposited thin film layers on the top silicon surface. During thermal cycle testing, thermomechanical stresses resulting from differences in expansion coefficient can cause large relative displacements at the silicon/mold compound interface. The resulting die surface shear stresses are heavily concentrated at the corners and edges of the silicon die. These shear stresses can result in critical stress concentrations in the brittle passivation and interlayer dielectric films. This paper will report on a test chip design involving a matrix of crossing metal traces. This test chip has been designed to be sensitive to electrical leakage problems associated with thin film cracking. Two important quantities are measured. The first is electrical failure rate, which is determined as a function of metal width and proximity to the corners and edges of the die. The second is the extent over which cracking in the thin film layers progresses into the interior of the die. When overlaid on simple linear elastic finite elements models of stress, this locus of failure tends to follow lines of constant shear stress. This allows the assignment of a nominal stress value, critical in the collapse of microscopic thin film structures

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:18 ,  Issue: 3 )

Date of Publication:

Aug 1995

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