By Topic

Hybrid Josephson-CMOS FIFO

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Feldman, A.R. ; Dept. of Electr. Eng., California Univ., Berkeley, CA, USA ; Van Duzer, T.

We describe the design of a hybrid Josephson-CMOS first-in-first-out memory (FIFO) for communications and signal processing applications. The FIFO takes advantage of high speed Josephson logic and dense CMOS memory. We focus on the low power CMOS ring pointer architecture employing a dual-port CMOS SRAM array and illustrate how a high speed Josephson demultiplexor-multiplexor pair can greatly increase throughput. We describe a novel eight transistor dual-port CMOS SRAM cell with low swing write and current-mode read with an asymmetric SQUID to perform differential current-sensing. Finally, we discuss the peripheral Josephson demultiplexor and multiplexor designed in edge-triggered logic.<>

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:5 ,  Issue: 2 )