By Topic

A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zhih-siou Cheng ; Department of Electrical Engineering, National Tsing Hua University, HsinChu, Taiwan, e-mail: ; Jenn-chyou Bor

A 64 dB gain range VGA with DC offset calibration loop is proposed in this work. This VGA adopts the degeneration type amplifier to vary voltage gain and uses the super-source-follower input stage to enhance the linearity. A digital-based DC offset calibration loop is also designed to solve the DC offset problem. An experimental chip is fabricated in 0.18 mum process. With 2 dB step, the gain error is less than 0.8 dB and the output DC offset is less than 100mV at maximum gain setting. The total power consumption is 11 mW

Published in:

2006 International Symposium on VLSI Design, Automation and Test

Date of Conference:

26-28 April 2006