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Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic

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1 Author(s)
Pramod Kumar Meher ; Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:53 ,  Issue: 12 )