Referenced Items are not available for this document.
In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-mum CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:53
,
Issue:
12
)
Date of Publication: Dec. 2006
- Page(s):
- 2647 - 2655
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 9238848
- Digital Object Identifier :
- 10.1109/TCSI.2006.885690
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 11 December 2006
- Issue Date :
- Dec. 2006
- Sponsored by :
- IEEE Circuits and Systems Society
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