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Fast Bit Parallel-Shifted Polynomial Basis Multipliers in GF(2n)

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2 Author(s)
Haining Fan ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont. ; M. Anwar Hasan

A new nonpipelined bit-parallel-shifted polynomial basis multiplier for GF(2n) is presented. For some irreducible trinomials, the space complexity of the multiplier matches the best results available in the literature, and its gate delay is equal to T A+lceillog2nrceilTX, where TA and TX are the delay of one two-input and and xor gates, respectively. To the best of our knowledge, this is the first time that the gate delay bound TA+lceillog2nrceilTX is reached. For some irreducible pentanomials, its gate delay is equal to TA +(1+lceillog2nrceil)TX. NIST has recommended five binary fields for the elliptic curve digital signature algorithm applications: GF(2163), GF(2233), GF(2 283), GF(2409), and GF(2571), but no irreducible trinomials exist for three degrees, viz., 163, 283 and 571. For the three corresponding binary fields, we show that the gate delay of the proposed multiplier is TA+(1+lceillog2nrceil)TX. This result outperforms the previously known results

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:53 ,  Issue: 12 )