Cart (Loading....) | Create Account
Close category search window
 

An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chuan He ; Texas A & M Univ., College Station, TX ; Guan Qin ; Mi Lu ; Wei Zhao

Finite difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. This paper introduces an efficient implementation of FD computing engine on FPGA-based reconfigurable computing (RC) platform. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floating point arithmetic units, a new class of optimized finite-accurate FD schemes was proposed, whose FD coefficients are optimized to be represented with only a few binary bits without deteriorating numerical accuracy criterions. Furthermore, in order to simplify the implementation of floating-point summations, the conventional costly floating-point adder tree was replaced by a floating-point/fixed-point hybrid accumulator using group-alignment technology. The resulting fully-pipelined FD computing engine with finite accurate coefficients can provide us similar or even better worst case relative and absolute rounding errors than standard floating-point arithmetic, but consumes only a fraction of hardware resources. This new design can be easily applied to our previous work (He et al., 2005) and result in a more efficient and compact implementation with higher computational performance

Published in:

Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on

Date of Conference:

Sept. 2006

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.