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A 1.9-GHz Single-Chip CMOS PHS Cellphone

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12 Author(s)
Si, W.W. ; Atheros Commun., Santa Clara, CA ; Mehta, S. ; Samavati, H. ; Terrovitis, M.
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A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 12 )