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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

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3 Author(s)
Gupta, S.K. ; Teranetics Inc., Santa Clara, CA ; Inerfield, M.A. ; Jingbo Wang

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented. To eliminate timing skews, a Nyquist rate sampling switch is used, which is followed by subsampled, double-sampled time-interleaved sample-and-hold (S/H) stages. This circuit is configured with a special clocking scheme that reduces the loading of the interleaved S/Hs on the Nyquist rate sampling switch, making this scalable to high sampling rates. The subsampled ADCs (sub-ADCs) in this design use a 3.5-bit/stage pipelined architecture. This 1-GS/s 11-bit ADC achieves 55-dB peak SNDR, 58.6-dB SNR, consumes 250-mW core power, and occupies a core area of 3.5 mm2. This circuit is implemented in a dual-gate 1.2 V/2.5 V, 0.13-mum logic CMOS process

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 12 )

Date of Publication:

Dec. 2006

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