Referenced Items are not available for this document.
Modern, high-performance processors employ techniques such as superscalar execution and super-pipelining to increase their instruction issue rate. As the instruction issue rate of processors increases, however, the negative impact of branches on performance also increases. This paper describes an instruction cache (I-cache) prefetch mechanism to improve processor performance on the taken branches. Under perfect conditions, the mechanism allows the target of a taken branch to be prefetched early enough to completely hide the memory latency of an I-cache miss
Published in:
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Date of Conference: 3-6 Oct 1993
- Page(s):
- 44 - 49
- Meeting Date :
- 03 Oct 1993-06 Oct 1993
- Print ISBN:
- 0-8186-4230-0
- INSPEC Accession Number:
- 4955841
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ICCD.1993.393407
- Product Type:
- Conference Publications
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