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A comparison of synchronous and asynchronous FSMD designs

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3 Author(s)
Auletta, R. ; Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA ; Reese, B. ; Traver, C.

This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data-path (FSMD) ASICs. The comparison is made through independent parallel designs of a 16-bit factoring ASIC. A common functional specification, standard cell library, and suite of EDA tools for layout and simulation are used to provide a common basis for comparison. To clarify design goals and provide more data for comparison each design is separately optimized for speed and for area. Timing and area information for each design is tabulated and discussed to illustrate the specific advantages and disadvantages of each approach

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993