A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture

A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuitry or latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry-propagation circuit is constructed only with simple selector circuits. A 54/spl times/54-bit multiplier is designed using 0.5-/spl mu/m CMOS technology. A multiplication time of 8.8 ns is obtained by SPICE2 simulation for a supply voltage of 3.3 V which is the fastest that has been reported for 54/spl times/54-bit multipliers.<
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