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Reducing the cost of test pattern generation by information reusing

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3 Author(s)
W. Li ; Dept. of Comput. Sci., Saskatchewan Univ., Saskatoon, Sask., Canada ; C. McCrosky ; M. Abd-El-Barr

A new source of computational saving for test pattern generation, i.e., information reusing, is presented. The proposed technique can make full use of the pattern generation information from the last pattern to derive a set of new tests by means of critical path transitions. By so doing, fault propagation procedure is no longer required in the next pattern generation process and the line justification procedure is simplified. Experiments using the ISCAS-85 benchmark circuits show that when the technique is used with a deterministic test pattern generation algorithm (DTPG), computational cost is greatly reduced without a substantial increase in test length

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993