By Topic

Analysis and control of timing jitter in digital logic arising from noise voltage sources

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lin, P.-S. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Zukowski, C.A.

Timing jitter is an important factor in limiting throughput in high-performance digital circuits, e.g. those using techniques such as wave pipelining. Many of the sources of timing jitter, such as physical noise, coupling noise, and delta-I noise, are best modeled with random shifts in signal voltages. A new analysis technique for translating such noise into timing jitter characteristics is presented. The circuit is linearized about its nominal behavior and the resulting time-varying system is discretized so that the mapping from voltage noise to timing jitter can be easily calculated and characterized. In addition, the use of differential circuit techniques to improve noise immunity is discussed

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993