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Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation

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4 Author(s)

We describe the design of Ravel-XL, a hardware accelerator for assigned-delay compiled-code logic gate simulation. After a brief review of the underlying Ravel simulation algorithm, we describe the major factors that influenced the hardware design, particularly the interaction between the instruction execution and operand bandwidth requirements. The initial CMOS VLSI implementation of the accelerator contains a 2K word data cache, occupies approximately 1.9 cm2 of die area with 256 pins and approximately 900,000 transistors. Simulation results predicts operation at a clock rate of 33 MHz. This provides a speedup of about 50 over the software implementation of Ravel, about 50 over a compiled event-driven simulator, and about 500 over an interpreted event-driven simulator. We conclude with some planned design improvements that will allow an approximate doubling of the clock rate

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993

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