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In this paper a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates circuits to determine the critical transistors that are most susceptible to hot-carrier effects (HCE); it then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE degradation on the performance. The advantages and disadvantages of these alternative designs are also compared
Published in:
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Date of Conference: 3-6 Oct 1993
- Page(s):
- 534 - 537
- Meeting Date :
- 03 Oct 1993-06 Oct 1993
- Print ISBN:
- 0-8186-4230-0
- INSPEC Accession Number:
- 4955928
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ICCD.1993.393320
- Product Type:
- Conference Publications
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