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Complex gate performance improvement by jog insertion into transistor gates

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1 Author(s)
Hindmarsh, R.D. ; Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany

This paper describes how the insertion of 45 degree jogs into transistor gates leads to performance improvement of static CMOS complex gates. Therefore, CMOS complex gates were designed using a new layout style called Jogged Gate Matrix Layout (JOGM). SPICE3 simulation results exhibit an up to 44% speed improvement in comparison to traditional gate matrix layout style, due to reduced diffusion capacitances. JOGM also improves cell width by up to 31%

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993

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