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Development of parallelism for circuit simulation by tearing

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5 Author(s)
Onozuka, H. ; ULSI Syst. Dev. Lab., NEC Corp., Kawasaki, Kanagawa, Japan ; Kanoh, M. ; Mizuta, C. ; Nakata, T.
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A hierarchical clustering with min-cut exchange method for parallel circuit simulation is presented. Partitioning into subcircuits is near optimum in terms of distribution of computational cost and does not sacrifice the sparsity of the entire matrix. In order to compute the arising dense interconnection matrix in parallel, multilevel and distributed row-base dissection algorithms are used. A processing speed up of 28 with 64 processors was achieved in large scale DRAM simulations

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993