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Automatic generation algorithms, experiments and comparisons of self-checking PLA schemes using parity codes

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3 Author(s)
M. Boudjit ; Reliable Integrated Syst. Group, IMAG/TIMA, Grenoble, France ; M. Nicolaidis ; K. Torki

Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is that they involve a significant increasing of the circuit area. Recent experiments on Berger-code encoded PLAs result on 46.9% average area overhead. In order to decrease this overhead, the authors present a tool that generates self-checking PLAs using parity encoding for the product terms and the outputs. This tool has been used for experimenting on several benchmark PLAs. In these experiments the authors retain for each PLA case the scheme involving the lower area overhead. Thus the mean overhead is reduced from 46.9% [TCR 91] to 37.2% (24.9% if a PLA named misex3 is not included)

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993